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KB-5295

IU Test b–f Command Pack — 09 Infra Closure Backlog and Sequencing

10 min read Revision 1
iubacklogsequencingU1-U11command-pack2026-05-28

09 — Infra Closure Backlog and Sequencing (U1–U11)

Ordered backlog to take IU from "survey accepted" to "tests b–f pass + production-ready brick". Impl type: read-only / mutating / design-only. Parallel?: can run concurrently with prior items or must wait.

1. Backlog

U1 — Read-only test harness (b/c + f-read)

  • Why: no end-to-end automated, evidence-producing test runner exists.
  • Dependent tests: b, c, f(read).
  • Live substrate: iu_three_axis_envelope, iu_metadata_tag(_registry), fn_iu_subtree, iu_tree_path, iu_relation, fn_iu_sql_link_validate, v_iu_sql_link_resolved.
  • Exact gap: dot_iu_filter_axis_b, dot_iu_subtree, dot_iu_sql_link_validate/resolve, dot_iu_test_harness_run (read-only core).
  • Law owner: Điều 38/39, Điều 35. Impl type: read-only (SELECT + audit rows). Mutation risk: none.
  • Macro: IU_TEST_B_C_READONLY_HARNESS_IMPLEMENTATION_XHIGH (+ f-read folded in or M2). Parallel?: yes (no gate). Risk if skipped: b–f never become demonstrable; readiness stays asserted not proven.

U2 — Bounded gate protocol

  • Why: mutating tests need a safe open/close primitive; none exists.
  • Dependent tests: d, e, f(enable).
  • Live substrate: dot_config, dot_iu_command_run, SSH workflow_admin channel.
  • Exact gap: the protocol fn(s)/runbook + watchdog + verify-close (deliverable 08).
  • Law owner: Điều 32 (approval to open), Điều 35 (audit). Impl type: mutating (gate-flip primitives only). Mutation risk: medium (gate flips) — mitigated by fail-closed + verify-close.
  • Macro: IU_BOUNDED_GATE_PROTOCOL_DESIGN_OR_IMPLEMENTATION_XHIGH. Parallel?: can be designed in parallel with U1; implementation waits on approval. Risk if skipped: any d/e attempt either fails or leaves gates open (Điều 32/45 violation).

U3 — Split/merge review_decision wiring

  • Why: fn_iu_piece_split/merge exist but iu_enact.allow_no_review_decision=false; governed REVIEW sub-pipeline + row-builder "never committed" (TD-P1 OPEN); iu_split_set/iu_merge_set empty.
  • Dependent tests: d (d5/d6).
  • Live substrate: cutter_governance.review_decision (exists; shape needs privileged read), fn_iu_piece_split/merge, iu_split_set, iu_merge_set.
  • Exact gap: commit the row-builder + governed review sub-pipeline that issues review_decision_id; wire split/merge to require it.
  • Law owner: Điều 32. Impl type: mutating. Mutation risk: medium-high. Macro: IU_SPLIT_MERGE_REVIEW_DECISION_WIRING_XHIGH. Parallel?: must wait for U2. Risk if skipped: d stays PARTIAL; split/merge unprovable; first-use of split/merge sets impossible.

U4 — Post-CUT autowire

  • Why: fn_iu_post_cut_axis_materialize exists but is not auto-invoked inside cut completion (G2 reclassified "exists, not auto-wired").
  • Dependent tests: a (hardening), b/c (fresh envelopes after cut).
  • Live substrate: fn_iu_post_cut_axis_materialize, iu.post_cut.axis_materialize, fn_cut_apply.
  • Exact gap: call autowire from cut completion with an idempotency key (namespace dot.iu_post_cut_axis_materialize).
  • Law owner: Điều 38/39, Điều 45 (idempotency). Impl type: mutating. Mutation risk: low-medium. Macro: part of a cut-hardening macro (post-M1). Parallel?: independent of d/e; can follow M1. Risk if skipped: axis envelopes drift after cuts; b/c need manual refresh.

U5 — Cut state-machine rollback edge

  • Why: no mark_verified→mark_rejected edge; cut_request can stick at mark_verified with cut_run_id=NULL.
  • Dependent tests: d (clean failure recovery if split/merge route through cut state machine).
  • Live substrate: cut_request, cut_request_transition, fn_cut_verify_mark, fn_cut_apply.
  • Exact gap: add the rollback transition + policy.
  • Law owner: Điều 30 (reversibility), Điều 45 (state machine). Impl type: mutating. Mutation risk: medium. Macro: IU_CUT_STATE_MACHINE_ROLLBACK_AFTER_APPROVAL_POLICY (already named as a next pack). Parallel?: independent; prerequisite for d's failure path. Risk if skipped: a failed split/merge cut can wedge the state machine with no recovery.

U6 — iu.* event-type registration

  • Why: no per-IU trigger contract types in event_type_registry (31 types, none iu.*).
  • Dependent tests: e.
  • Live substrate: event_type_registry, fn_iu_emit_event, fn_iu_piece_emit_event.
  • Exact gap: register iu.trigger_in.received, iu.trigger_out.emitted, iu.route.delivered, iu.route.failed with JSON schemas, compat_mode=forward, refs-only payloads.
  • Law owner: Điều 45. Impl type: mutating (registry rows). Mutation risk: low (additive, register-before-emit). Macro: IU_TRIGGER_IN_OUT_EVENT_CONTRACT_AND_TEST_PLAN_XHIGH. Parallel?: can register in parallel with U1/U2; e run waits on U2. Risk if skipped: e is BLOCKED; or unschema'd events pollute the bus.
  • Why: read-only filter/sql-link verbs absent from the 42-command catalog.
  • Dependent tests: b, c, f.
  • Exact gap: the read-only commands in deliverable 07 (folded into U1/M2).
  • Law owner: Điều 35. Impl type: read-only. Mutation risk: none. Macro: M1/M2. Parallel?: yes. Risk if skipped: b/c/f not DOT-callable (fail the "DOT-callable" acceptance criterion).

U8 — IU process-binding layer (for 4 Mothers, NOT b–f)

  • Why: iu_process_binding, iu_assembly_slot_registry, iu_role_in_process are genuinely paper; needed by the 4 Mothers.
  • Dependent tests: none of b–f (orthogonal).
  • Exact gap: assemble binding tables over existing live data.
  • Law owner: Điều 38/39 + future Điều XX. Impl type: mutating (new tables). Mutation risk: medium. Macro: post-b–f, pre-4-Mothers. Parallel?: must wait until b–f close. Risk if skipped: 4 Mothers re-invent body/ordering storage (R1 duplicate fields).

U9 — Queue-hardening registries

  • Why: executor_class_registry, state_machine_registry, idempotency_registry, retry_policy_registry, dlq_replay_request absent; needed for factory-scale safety.
  • Dependent tests: not required for b–f PASS; required for production e + 4 Mothers.
  • Exact gap: survey → design → implement these registries.
  • Law owner: Điều 45. Impl type: mutating. Mutation risk: medium. Macro: IU_EVENT_QUEUE_SUBSTRATE_READINESS_FOR_IU_PRODUCTION (Gate C). Parallel?: can survey in parallel; implement after b–f. Risk if skipped: 148k-row bus has no generic retry/poison/replay governance (R4).

U10 — Candidate registries (CRS)

  • Why: field_registry, input_form_registry, output_table_registry, dot_function_registry, tier_registry absent; MOIT/MOUT io_contract_refs + MOUT aggregation depend on them; MP-D7 forbids literal-name reference until verified_live.
  • Dependent tests: f (MOUT aggregation only), 4 Mothers.
  • Exact gap: Candidate Registry Survey (Gate B) then implement.
  • Law owner: Điều 35/28. Impl type: design-only (survey) then mutating. Macro: IU_4MOTHERS_CANDIDATE_REGISTRY_SURVEY. Parallel?: survey in parallel. Risk if skipped: CRS contract drift (R5).

U11 — Design PG-Maximization-Map reconciliation

  • Why: design docs mislabel verified_live artifacts as "paper" (deliverable 01).
  • Dependent tests: none directly; prevents 4 Mothers from re-proposing live substrate.
  • Exact gap: surgical drift patch to 00-master-design-rev2.md §10 (re-label, rename iu_kg_edge→iu_relation, reclassify G2). NOT a redesign.
  • Law owner: doc governance. Impl type: design-only (patch). Mutation risk: none. Macro: surgical drift patch. Parallel?: anytime. Risk if skipped: 4 Mothers design duplicates existing tables.

2. Sequencing (dependency-ordered)

Wave 0 (parallel, no gate):   U1 (b/c + f-read harness)  ||  U7 (read DOT cmds, in U1)  ||  U11 (doc patch)  ||  U10 survey  ||  U9 survey
Wave 1 (design+approve):      U2 (bounded gate protocol)        ||  U6 (iu.* event registration)
Wave 2 (mutating, gated):     U3 (review_decision wiring) → d5/d6 ;  U5 (state-machine rollback)  ;  U4 (post-cut autowire)
Wave 3 (gated test runs):     d (full)  via U2+U3(+U5)  ;  e (full) via U2+U6
Wave 4 (productionize):       U9 implement ; U10 implement ; then U8 (process-binding) — pre-4-Mothers
Wave 5:                       4 Mothers (only after b–f close/accepted)

Critical path to "b–f demonstrable": U1 → (U2 ∧ U6) → U3 → d/e runs. b, c, f(read) are PASS-able at end of Wave 0 alone.

3. What can be parallelized vs must wait

  • Parallel now (zero gate): U1, U7, U10-survey, U9-survey, U11.
  • Design in parallel, implement on approval: U2, U6.
  • Strictly sequential: U3 after U2; d-run after U2∧U3(∧U5); e-run after U2∧U6.
  • Deferred to post-b–f: U8, U9-implement, U10-implement, then 4 Mothers.
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